In this three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS. This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this class, students should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven constrained-random stimulus using VCS.
To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.
|Build a SystemVerilog verification environment|
|Define testbench components using object-oriented programing|
|Develop a stimulus generator to create constrained random test stimulus|
|Develop device driver routines to drive DUT input with stimulus from generator|
|Develop device monitor routines to sample DUT output|
|Develop self-check routines to verify correctness of DUT output|
|Abstract DUT stimulus as data objects|
|Execute device drivers, monitors and self-checking routines concurrently|
|Communicate among concurrent routines using events, semaphores and mailboxes|