This course consists of two sub-courses:
- Crosstalk and Noise Analysis
This workshop teaches the basic concepts of crosstalk and their effects on timing and noise. You learn how to identify and examine these crosstalk effects, as well as how to perform “what-if” analysis to guide the place and route tools in the fixing of violations. You apply the PrimeTime SI flow and methodology for chip-level crosstalk analysis. The labs enable you to analyze crosstalk failures.
This class teaches best-practice methodologies, enabling you to drive the PrimeTime SI tool at its optimum performance. Hands-on labs follow each training module, allowing you to apply the skills learned in lecture.
- Static Timing Analysis
This workshop shows you how to maximize your productivity when using PrimeTime. Topics include preparing for STA on your design, including investigating and analyzing the clocks that dictate STA results; identifying opportunities to improve run time; and performing static timing analysis. This workshop focuses on the SPEF- based flow, but also covers issues relating to SDF back annotation.
|Run PTSI for crosstalk delay and noise analysis|
|Use the key reports in the shell and GUI to identify violations due to crosstalk, and to guide timing closure|
|Define clock relationships for improved timing accuracy|
|Apply useful commands to catch and report incomplete inputs to PTSI|
|More finely control PTSI and your fixing tool using the following techniques|
|Manually control delta delay and noise calculations for specific nets|
|Apply path-based analysis|
|Apply what-if analysis, both automatically and manually|
|Interpret the essential details in a timing report for setup and hold, recovery and removal, and clock-gating setup and hold|
|Generate timing reports for specific paths and with specific details|
|Generate summary reports of the design violations organized by clock, slack, or by timing check|
|Create, execute, and debug a PrimeTime run script|
|Create a saved session and subsequently restore the saved session|
|Identify the clocks, where they are defined, and which ones interact, on an unfamiliar design|
|Prepare for performing STA on a design and then use this knowledge to respond to, focus, and debug your timing analysis|